1. Technical Field
The present invention relates generally to semiconductor design technology, and more particularly, to an exclusive OR circuit.
2. Related Art
A semiconductor apparatus is designed using a plurality of logic circuits. Among the plurality of logic circuits, an exclusive OR circuit may be widely used in the circuit design field in areas such as data parity bit schemes, particularly Error Correcting Code (ECC) and Cyclical Redundancy Check (CRC), in order to increase reliability. Such a circuit may also be applied to various design fields such as Application Specific Integrated Circuits (ASIC), communication design, graphic DRAM, as well as DRAM.
FIG. 1 is a diagram illustrating a unit circuit diagram of a conventional exclusive OR circuit.
The conventional exclusive OR circuit includes a first OR gate OR1, a first NAND gate ND1, and a first AND gate AD1.
The first OR gate OR1 and the first NAND gate ND1 are configured to receive first and second data A and B and perform the corresponding logic operation on the received data.
The first AND gate AD1 is configured to perform a logic operation on outputs of the first OR gate OR1 and the first NAND gate ND1 and output the operation result as final data C.
The exclusive OR circuit receives the first and second data A and B and obtains the following operation results.
First data ASecond data BFinal data C000011101110
The circuit illustrated in FIG. 1 operates as a general exclusive OR circuit which outputs a high level when two complementary data are received.
Semiconductor apparatuses have developed according to is the trend of low voltage, high integration, and small size. However, since the above-described exclusive OR circuit includes a large number of transistors, the design efficiency decreases. For example, the area of a semiconductor chip may be increased, or the data processing time may be delayed.